Active Compensation of Parasitic Capacitances for Very High Frequency CMOS DACs
نویسندگان
چکیده
High frequency DACs requiring an output buffer find a speed limitation in the overall input capacitive load of the buffer. This communication presents an active scheme for the compensation of such a load, including the parasitic capacitances coming from reversely biased junctions associated to analog switches. Computer simulations on a given architecture (10-bit DAC) show the effectiveness of the proposed approach.
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